It can be appreciated that several trends presently exist in the electronics industry. Devices are continually getting smaller, faster and requiring less power, while simultaneously being able to support and perform a greater number of increasingly complex and sophisticated functions. One reason for these trends is an ever increasing demand for small, portable and multifunctional electronic devices such as cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market.
Accordingly, there is a continuing trend in the semiconductor industry to manufacture integrated circuits (ICs) with higher device densities by scaling down dimensions (e.g., at submicron levels) on semiconductor wafers. To accomplish such high densities, smaller feature sizes, smaller separations between features and layers, and/or more precise feature shapes are required, such as metal interconnects or leads, for example. The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication processes by providing or ‘packing’ more circuits on a semiconductor die and/or more die per semiconductor wafer, for example.
One way to increase packing densities is to decrease the thickness of transistor gate dielectrics to shrink the overall dimensions of transistors used in IC's and electronic devices. Transistor gate dielectrics (e.g., silicon dioxide or nitrided silicon dioxide) have recently been reduced considerably to reduce transistor sizes and facilitate improved performance. Thinning gate dielectrics can have certain drawbacks, however. For example, a polycrystalline silicon (“polysilicon”) gate overlies the thin gate dielectric, and polysilicon naturally includes a depletion region where it interfaces with the gate dielectric. This depletion region can provide an insulative effect rather than conductive behavior, which is desired of the polysilicon gate since the gate is to act as an electrode for the transistor.
By way of example, if the depletion region acts like a 0.8 nm thick insulator and the gate dielectric is 10-nm thick, then the depletion region effectively increases the overall insulation between the gate and an underlying transistor channel by eight percent (e.g., from 10 nm to 10.8 nm). It can be appreciated that as the thickness of gate dielectrics are reduced, the effect of the depletion region can have a greater impact on dielectric behavior. For example, if the thickness of the gate dielectric is reduced to 2 nm, the depletion region would effectively increase the gate insulator by about 40 percent (e.g., from 2 nm to 2.8 nm). This increased percentage significantly reduces the benefits otherwise provided by thinner gate dielectrics.
Metal gates can be used to mitigate adverse effects associated with the depletion region phenomenon because, unlike polysilicon, little to no depletion region manifests in metal. Interestingly enough, metal gates were commonly used prior to the more recent use of polysilicon gates. An inherent limitation of such metal gates, however, led to the use of polysilicon gates. In particular, the use of a single work function metal proved to be a limitation in high performance circuits that require dual work function electrodes for low power consumption. The work function is the energy required to move an electron from the Fermi level to the vacuum level, in modern CMOS circuits, for example, both p-channel MOS transistor devices (“PMOS”) and n-channel MOS transistor devices (“NMOS”) are generally required in the same device, where a PMOS transistor requires a work function on the order of 5 eV and an NMOS transistor requires a work function on the order of 4 eV. A single metal can not be used, however, to produce a metal gate that provides such different work functions. Polysilicon gates are suited for application in CMOS devices since some of the gates can be substitutionally doped in a first manner to achieve the desired work function for PMOS transistors and other gates can be substitutionally doped in a second manner to achieve the desired work function for NMOS transistors. However, polysilicon gates suffer from the aforementioned gate depletion.
Fully silicided (FUSI) gates eliminate the problem of polysilicon depletion. FUSI gates also increase the gate conductance (lower resistance) that can further improve device performance. A FUSI gate can be formed by depositing a metal layer (e.g., Ni, Ti, Co, Pt, W) over an exposed polysilicon gate region, pre-annealing (e.g., a rapid thermal process, RTP) to provide the required diffusion of the metal info the polysilicon, removing the unreacted metal, and then annealing the semiconductor structure to form a more stable silicide alloy phase. The deposited metal reacts with the exposed polysilicon gate to transform the polysilicon gate fully into a silicided gate. Preferably, the FUSI gate structure is then topped off with a low resistance contact.
The FUSI gate silicide is produced by an interaction between the diffused metal and silicon or polysilicon to produce a metal-silicon alloy such as NiSi. The process of forming a silicide is known as silicidation, and generally includes some type of heat treatment (e.g., annealing, sintering) to cause the metal and silicon to react with one another and form the more stable silicide alloy phase. Silicides generally have a low resistivity and thus perform well as gate contacts in transistors. A “silicide” is a self-aligned silicide formed atop a silicon gate. The silicide is said to be self-aligned, or a salicide, because it only reacts with the underlying silicon gate structure and thus does not generally extend off onto other structures, such as insulative sidewall spacers.
FUSI gates normally have a work function near the middle of the silicon bend structure. However, CMOS devices normally require a conductive gate with a work function near the band edge; i.e., near the conduction band for an NMOS device and near the valence band for a PMOS device, respectively. Thus, for CMOS technologies with FUSI gates, the different work functions required for each of the NMOS and PMOS portions of the CMOS device present a fabrication challenge as both types are usually required in the same device and may also require different dopant species in the doping process.
In addition, the silicide typically forms at different rates in the NMOS and PMOS devices to the point where it may be difficult to obtain a controllable or stable silicidation process. Because of these differing formation rates and the instability of the conventional process, the gate silicide formation occurring in a PMOS transistor may be yet incomplete, while an NMOS type transistor in the same device may have excessively formed and punched through the gate oxide layer.
Consequently, it would be desirable to be able to provide a more evenly matched formation of a fully silicided gate in both NMOS and PMOS regions of the same MOS device.